计算机组成与嵌入式系统 pdf epub mobi txt 电子书 下载 2026
出版者:机械工业出版社
作者:（加）Carl Hamacher
出品人:
页数:710
译者:
出版时间:2013-1-1
价格:69.00元
装帧:平装
isbn号码:9787111377214
丛书系列:经典原版书库
图书标签:
- 计算机组成
- 计算机科学
- 专业书籍
- 计算机硬件
- ;Computer
- 体系结构
- Science
- 计算机组成原理
- 嵌入式系统
- 计算机体系结构
- 数字逻辑
- 汇编语言
- 硬件设计
- 系统设计
- 单片机
- ARM
- RISC-V
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具体描述
本书是一本经典的计算机组成教材，自1978年问世以来，已被多所世界知名大学选为教材。本书知识结构合理，知识点全面完整，基本概念广泛而新颖。书中不仅介绍了硬件设计的原理，说明了硬件设计如何受软件需求影响，而且以流行的商用处理器作为范例，描述了各种基本知识和基本概念的应用方法和应用过程，具有很强的实用性。此外，本书还涵盖了当今许多先进的技术和设计思想。
本书特色
系统地介绍了现代计算机硬件系统的各个组成部分，包括处理器、输入/输出、存储器和互连标准等。
以Nios II、ARM、ColdFire和Intel IA-32等商用处理器为例来阐释基本概念，侧重于讨论RISC设计风格的处理器（如MIPS），同时也介绍了CISC设计风格的处理器（如应用比较广泛的商用处理器Intel IA-32）。
《穿梭时空的密码：一个文明的演进与重塑》 这是一部探索人类文明脉络与未来走向的史诗级巨著。作者以其深邃的历史洞察力和前瞻性的社会构想，将我们带入一场跨越千年、融汇东西的宏大叙事。本书并非简单罗列史实，而是致力于揭示隐藏在事件表象之下的驱动力，剖析那些塑造我们世界观、价值观和生活方式的深层密码。 第一篇：文明的起源与黄金时代的曙光 本书伊始，我们将追溯人类文明的萌芽，从早期社会结构、语言的诞生、文字的出现，到第一个伟大文明——美索不达米亚的崛起，再到古埃及的辉煌、古希腊的思想解放以及古罗马的法律与工程成就。作者细致地描绘了这些文明如何孕育出独特的哲学、艺术、科学和政治体系，为后世奠定了坚实的基础。特别地，我们将深入探讨古希腊的理性精神如何影响了西方思想的形成，以及中国早期哲学如儒家、道家等如何塑造了东方社会的伦理道德观。 接着，我们将目光投向被誉为“黄金时代”的时期。从中世纪欧洲的知识复苏，到伊斯兰世界的科学繁荣，再到中国的宋代科技高峰，作者展现了不同文明在特定历史阶段迸发出的惊人创造力。阿拉伯学者如何保存并发展了古希腊的知识，丝绸之路如何促进了东西方文明的交流，中国四大发明的深远影响，这些章节都将以生动详实的笔触呈现。 第二篇：变革的浪潮与全球化的初啼 随着地理大发现的开启，世界格局开始发生翻天覆地的变化。本书将详细阐述欧洲文艺复兴、宗教改革以及启蒙运动如何颠覆了旧有的世界秩序，催生了现代科学、政治思想和经济模式。我们将看到哥白尼的日心说如何挑战了教会的权威，洛克的自由思想如何奠定了现代民主的基石，亚当·斯密的经济理论如何开启了资本主义的新篇章。 同时，工业革命的到来无疑是人类历史上最深刻的转折点之一。作者将深入剖析蒸汽机的发明、工厂制度的建立以及机械化生产的普及如何彻底改变了人类的生产方式、社会结构和生活节奏。从英国的棉纺织业到德国的钢铁工业，再到美国的铁路建设，我们将看到技术创新如何推动社会进步，也反思其带来的阶级分化、环境污染等负面影响。 全球化进程的加速，使得不同文明之间的联系日益紧密，同时也带来了新的挑战与冲突。本书将探讨殖民主义的兴衰，民族主义的兴起，以及两次世界大战对人类文明的重创与反思。我们将看到，科技的进步与战争的残酷并存，人类在追求进步的同时，也必须面对其可能带来的毁灭性后果。 第三篇：数字时代的回响与未来的远眺 进入20世纪下半叶，信息革命以前所未有的速度席卷全球。本书将聚焦于计算机技术的发明与发展，互联网的普及，以及信息时代的到来。我们将深入理解数据如何成为新的生产要素，人工智能、大数据、云计算等前沿技术如何重塑我们的生活、工作乃至思维方式。 作者将以独特的视角，分析数字技术如何影响着社会治理、经济模式、文化传播乃至个体身份的认知。从社交媒体的兴起如何改变人际互动，到电子商务的蓬勃发展如何重塑商业生态，再到智能制造如何引领工业4.0的浪潮，本书都将给予深入的解读。 展望未来，本书将触及人类文明可能面临的机遇与挑战。气候变化、资源枯竭、人工智能的伦理困境、全球治理的复杂性，这些议题都将被置于显微镜下进行审视。作者并非预言家，而是倡导一种积极的、负责任的态度，鼓励我们通过跨学科的合作、跨文化的对话，共同探索可持续发展的道路，重塑一个更加公正、繁荣和富有韧性的未来文明。 《穿梭时空的密码：一个文明的演进与重塑》是一场关于我们是谁、我们从哪里来、我们将去往何方的深刻思考。它是一份献给所有对历史充满好奇、对未来怀有憧憬的读者的礼物，引导我们拨开迷雾，理解文明的精髓，并为构建更美好的明天贡献智慧与力量。
作者简介
Carl Hamacher 女皇大学电子工程与计算机系荣誉退休教授，曾担任女皇大学应用科学系主任，多伦多大学电子工程及计算机科学系教授、计算机系统研究所所长、工程科学部主席。他的研究兴趣是多处理器和多计算机，侧重于网络互连。
Zvonko Vranesic 多伦多大学电气与计算机工程系荣誉退休教授，曾参与Altera公司多伦多技术中心的研究和开发工作。他代表加拿大参加过多次国际象棋比赛，拥有国际象棋大师的头衔。他的研究兴趣是计算机体系结构、现场可编程超大规模集成电路技术和多值逻辑系统。
Safwat Zaky 多伦多大学电气与计算机工程系荣誉退休教授，并且曾担任该系系主任。他的研究兴趣是计算机体系结构、数字电路设计和电磁兼容性。
Naraig Manjikian 女皇大学电子工程与计算机系副教授，他的研究兴趣是计算机体系结构、多处理器系统、现场可编程超大规模集成电路技术和并行处理技术应用。
目录信息
C h a p t e r 1
Basic Structure of
Computers 1
1.1 Computer Types 2
1.2 Functional Units 3
1.2.1 Input Unit 4
1.2.2 Memory Unit 4
1.2.3 Arithmetic and Logic Unit 5
1.2.4 Output Unit 6
1.2.5 Control Unit 6
1.3 Basic Operational Concepts 7
1.4 Number Representation and Arithmetic Operations 9
1.4.1 Integers 10
1.4.2 Floating-Point Numbers 16
1.5 Character Representation 17
1.6 Performance 17
1.6.1 Technology 17
1.6.2 Parallelism 19
1.7 Historical Perspective 19
1.7.1 The First Generation 20
1.7.2 The Second Generation 20
1.7.3 The Third Generation 21
1.7.4 The Fourth Generation 21
1.8 Concluding Remarks 22
1.9 Solved Problems 22
Problems 24
References 25
C h a p t e r 2
Instruction Set
Architecture 27
2.1 Memory Locations and Addresses 28
2.1.1 Byte Addressability 30
2.1.2 Big-Endian and Little-Endian Assignments 30
2.1.3 Word Alignment 31
2.1.4 Accessing Numbers and Characters 32
2.2 Memory Operations 32
2.3 Instructions and Instruction Sequencing 32
2.3.1 Register Transfer Notation 33
2.3.2 Assembly-Language Notation 33
2.3.3 RISC and CISC Instruction Sets 34
2.3.4 Introduction to RISC Instruction Sets 34
2.3.5 Instruction Execution and Straight-Line Sequencing 36
2.3.6 Branching 37
2.3.7 Generating Memory Addresses 40
2.4 Addressing Modes 40
2.4.1 Implementation of Variables and
Constants 41
2.4.2 Indirection and Pointers 42
2.4.3 Indexing and Arrays 45
2.5 Assembly Language 48
2.5.1 Assembler Directives 50
2.5.2 Assembly and Execution of Programs 53
2.5.3 Number Notation 54
2.6 Stacks 55
2.7 Subroutines 56
2.7.1 Subroutine Nesting and the Processor Stack 58
2.7.2 Parameter Passing 59
2.7.3 The Stack Frame 63
2.8 Additional Instructions 65
2.8.1 Logic Instructions 67
2.8.2 Shift and Rotate Instructions 68
2.8.3 Multiplication and Division 71
2.9 Dealing with 32-Bit Immediate Values 73
2.10 CISC Instruction Sets 74
2.10.1 Additional Addressing Modes 75
2.10.2 Condition Codes 77
2.11 RISC and CISC Styles 78
2.12 Example Programs 79
2.12.1 Vector Dot Product Program 79
2.12.2 String Search Program 81
2.13 Encoding of Machine Instructions 82
2.14 Concluding Remarks 85
2.15 Solved Problems 85
Problems 90
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Contents
C h a p t e r 3
Basic Input/Output 95
3.1 Accessing I/O Devices 96
3.1.1 I/O Device Interface 97
3.1.2 Program-Controlled I/O 97
3.1.3 An Example of a RISC-Style I/O Program 101
3.1.4 An Example of a CISC-Style I/O Program 101
3.2 Interrupts 103
3.2.1 Enabling and Disabling Interrupts 106
3.2.2 Handling Multiple Devices 107
3.2.3 Controlling I/O Device Behavior 109
3.2.4 Processor Control Registers 110
3.2.5 Examples of Interrupt Programs 111
3.2.6 Exceptions 116
3.3 Concluding Remarks 119
3.4 Solved Problems 119
Problems 126
C h a p t e r 4
Software 129
4.1 The Assembly Process 130
4.1.1 Two-pass Assembler 131
4.2 Loading and Executing Object Programs 131
4.3 The Linker 132
4.4 Libraries 133
4.5 The Compiler 133
4.5.1 Compiler Optimizations 134
4.5.2 Combining ProgramsWritten in Different Languages 134
4.6 The Debugger 134
4.7 Using a High-level Language for I/O Tasks 137
4.8 Interaction between Assembly Language and C Language 139
4.9 The Operating System 143
4.9.1 The Boot-strapping Process 144
4.9.2 Managing the Execution of Application Programs 144
4.9.3 Use of Interrupts in Operating Systems 146
4.10 Concluding Remarks 149
Problems 149
References 150
C h a p t e r 5
Basic Processing Unit 151
5.1 Some Fundamental Concepts 152
5.2 Instruction Execution 155
5.2.1 Load Instructions 155
5.2.2 Arithmetic and Logic Instructions 156
5.2.3 Store Instructions 157
5.3 Hardware Components 158
5.3.1 Register File 158
5.3.2 ALU 160
5.3.3 Datapath 161
5.3.4 Instruction Fetch Section 164
5.4 Instruction Fetch and Execution Steps 165
5.4.1 Branching 168
5.4.2 Waiting for Memory 171
5.5 Control Signals 172
5.6 Hardwired Control 175
5.6.1 Datapath Control Signals 177
5.6.2 Dealing with Memory Delay 177
5.7 CISC-Style Processors 178
5.7.1 An Interconnect using Buses 180
5.7.2 Microprogrammed Control 183
5.8 Concluding Remarks 185
5.9 Solved Problems 185
Problems 188
C h a p t e r 6
Pipelining 193
6.1 Basic Concept—The Ideal Case 194
6.2 Pipeline Organization 195
6.3 Pipelining Issues 196
6.4 Data Dependencies 197
6.4.1 Operand Forwarding 198
6.4.2 Handling Data Dependencies in Software 199
6.5 Memory Delays 201
6.6 Branch Delays 202
6.6.1 Unconditional Branches 202
6.6.2 Conditional Branches 204
6.6.3 The Branch Delay Slot 204
6.6.4 Branch Prediction 205
6.7 Resource Limitations 209
6.8 Performance Evaluation 209
6.8.1 Effects of Stalls and Penalties 210
6.8.2 Number of Pipeline Stages 212
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Contents
6.9 Superscalar Operation 212
6.9.1 Branches and Data Dependencies 214
6.9.2 Out-of-Order Execution 215
6.9.3 Execution Completion 216
6.9.4 Dispatch Operation 217
6.10 Pipelining in CISC Processors 218
6.10.1 Pipelining in ColdFire Processors 219
6.10.2 Pipelining in Intel Processors 219
6.11 Concluding Remarks 220
6.12 Examples of Solved Problems 220
Problems 222
References 226
C h a p t e r 7
Input/Output Organization 227
7.1 Bus Structure 228
7.2 Bus Operation 229
7.2.1 Synchronous Bus 230
7.2.2 Asynchronous Bus 233
7.2.3 Electrical Considerations 236
7.3 Arbitration 237
7.4 Interface Circuits 238
7.4.1 Parallel Interface 239
7.4.2 Serial Interface 243
7.5 Interconnection Standards 247
7.5.1 Universal Serial Bus (USB) 247
7.5.2 FireWire 251
7.5.3 PCI Bus 252
7.5.4 SCSI Bus 256
7.5.5 SATA 258
7.5.6 SAS 258
7.5.7 PCI Express 258
7.6 Concluding Remarks 260
7.7 Solved Problems 260
Problems 263
References 266
C h a p t e r 8
The Memory System 267
8.1 Basic Concepts 268
8.2 Semiconductor RAM Memories 270
8.2.1 Internal Organization of Memory Chips 270
8.2.2 Static Memories 271
8.2.3 Dynamic RAMs 274
8.2.4 Synchronous DRAMs 276
8.2.5 Structure of Larger Memories 279
8.3 Read-only Memories 282
8.3.1 ROM 283
8.3.2 PROM 283
8.3.3 EPROM 284
8.3.4 EEPROM 284
8.3.5 Flash Memory 284
8.4 Direct Memory Access 285
8.5 Memory Hierarchy 288
8.6 Cache Memories 289
8.6.1 Mapping Functions 291
8.6.2 Replacement Algorithms 296
8.6.3 Examples of Mapping Techniques 297
8.7 Performance Considerations 300
8.7.1 Hit Rate and Miss Penalty 301
8.7.2 Caches on the Processor Chip 302
8.7.3 Other Enhancements 303
8.8 Virtual Memory 305
8.8.1 Address Translation 306
8.9 Memory Management Requirements 310
8.10 Secondary Storage 311
8.10.1 Magnetic Hard Disks 311
8.10.2 Optical Disks 317
8.10.3 Magnetic Tape Systems 322
8.11 Concluding Remarks 323
8.12 Solved Problems 324
Problems 328
References 332
C h a p t e r 9
Arithmetic 335
9.1 Addition and Subtraction of Signed Numbers 336
9.1.1 Addition/Subtraction Logic Unit 336
9.2 Design of Fast Adders 339
9.2.1 Carry-Lookahead Addition 340
9.3 Multiplication of Unsigned Numbers 344
9.3.1 Array Multiplier 344
9.3.2 Sequential Circuit Multiplier 346
9.4 Multiplication of Signed Numbers 346
9.4.1 The Booth Algorithm 348
9.5 Fast Multiplication 351
9.5.1 Bit-Pair Recoding of Multipliers 352
9.5.2 Carry-Save Addition of Summands 353
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9.5.3 Summand Addition Tree using 3-2 Reducers 355
9.5.4 Summand Addition Tree using 4-2 Reducers 357
9.5.5 Summary of Fast Multiplication 359
9.6 Integer Division 360
9.7 Floating-Point Numbers and Operations 363
9.7.1 Arithmetic Operations on Floating-Point Numbers 367
9.7.2 Guard Bits and Truncation 368
9.7.3 Implementing Floating-Point Operations 369
9.8 Decimal-to-Binary Conversion 372
9.9 Concluding Remarks 372
9.10 Solved Problems 374
Problems 377
References 383
C h a p t e r 10
Embedded Systems 385
10.1 Examples of Embedded Systems 386
10.1.1 Microwave Oven 386
10.1.2 Digital Camera 387
10.1.3 Home Telemetry 390
10.2 Microcontroller Chips for Embedded Applications 390
10.3 A Simple Microcontroller 392
10.3.1 Parallel I/O Interface 392
10.3.2 Serial I/O Interface 395
10.3.3 Counter/Timer 397
10.3.4 Interrupt-Control Mechanism 399
10.3.5 Programming Examples 399
10.4 Reaction Timer—AComplete Example 401
10.5 Sensors and Actuators 407
10.5.1 Sensors 407
10.5.2 Actuators 410
10.5.3 Application Examples 411
10.6 Microcontroller Families 412
10.6.1 Microcontrollers Based on the Intel 8051 413
10.6.2 Freescale Microcontrollers 413
10.6.3 ARM Microcontrollers 414
10.7 Design Issues 414
10.8 Concluding Remarks 417
Problems 418
References 420
C h a p t e r 11
System-on-a-Chip—A Case Study 421
11.1 FPGA Implementation 422
11.1.1 FPGA Devices 423
11.1.2 Processor Choice 423
11.2 Computer-Aided Design Tools 424
11.2.1 Altera CAD Tools 425
11.3 Alarm Clock Example 428
11.3.1 User’s View of the System 428
11.3.2 System Definition and Generation 429
11.3.3 Circuit Implementation 430
11.3.4 Application Software 431
11.4 Concluding Remarks 440
Problems 440
References 441
C h a p t e r 12
Parallel Processing and Performance 443
12.1 Hardware Multithreading 444
12.2 Vector (SIMD) Processing 445
12.2.1 Graphics Processing Units (GPUs) 448
12.3 Shared-Memory Multiprocessors 448
12.3.1 Interconnection Networks 450
12.4 Cache Coherence 453
12.4.1 Write-Through Protocol 453
12.4.2 Write-Back protocol 454
12.4.3 Snoopy Caches 454
12.4.4 Directory-Based Cache Coherence 456
12.5 Message-Passing Multicomputers 456
12.6 Parallel Programming for Multiprocessors 456
12.7 Performance Modeling 460
12.8 Concluding Remarks 461
Problems 462
References 463
A p p e n d i x A
Logic Circuits 465
A.1 Basic Logic Functions
A.1.1 Electronic Logic Gates 469
A.2 Synthesis of Logic Functions 470
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A.3 Minimization of Logic Expressions 472
A.3.1 Minimization using Karnaugh Maps 475
A.3.2 Don’t-Care Conditions 477
A.4 Synthesis with NAND and NOR Gates 479
A.5 Practical Implementation of Logic Gates 482
A.5.1 CMOS Circuits 484
A.5.2 Propagation Delay 489
A.5.3 Fan-In and Fan-Out Constraints 490
A.5.4 Tri-State Buffers 491
A.6 Flip-Flops 492
A.6.1 Gated Latches 493
A.6.2 Master-Slave Flip-Flop 495
A.6.3 Edge Triggering 498
A.6.4 T Flip-Flop 498
A.6.5 JK Flip-Flop 499
A.6.6 Flip-Flops with Preset and Clear 501
A.7 Registers and Shift Registers 502
A.8 Counters 503
A.9 Decoders 505
A.10 Multiplexers 506
A.11 Programmable Logic Devices (PLDs) 509
A.11.1 Programmable Logic Array (PLA) 509
A.11.2 Programmable Array Logic (PAL) 511
A.11.3 Complex Programmable Logic Devices (CPLDs) 512
A.12 Field-Programmable Gate Arrays 514
A.13 Sequential Circuits 516
A.13.1 Design of an Up/Down Counter as a Sequential Circuit 516
A.13.2 Timing Diagrams 519
A.13.3 The Finite State Machine Model 520
A.13.4 Synthesis of Finite State Machines 521
A.14 Concluding Remarks 522
Problems 522
References 528
A p p e n d i x B
The Altera Nios II
Processor 529
B.1 Nios II Characteristics 530
B.2 General-Purpose Registers 531
B.3 Addressing Modes 532
B.4 Instructions 533
B.4.1 Notation 533
B.4.2 Load and Store Instructions 534
B.4.3 Arithmetic Instructions 536
B.4.4 Logic Instructions 537
B.4.5 Move Instructions 537
B.4.6 Branch and Jump Instructions 538
B.4.7 Subroutine Linkage Instructions 541
B.4.8 Comparison Instructions 545
B.4.9 Shift Instructions 546
B.4.10 Rotate Instructions 547
B.4.11 Control Instructions 548
B.5 Pseudoinstructions 548
B.6 Assembler Directives 549
B.7 Carry and Overflow Detection 551
B.8 Example Programs 553
B.9 Control Registers 553
B.10 Input/Output 555
B.10.1 Program-Controlled I/O 556
B.10.2 Interrupts and Exceptions 556
B.11 Advanced Configurations of Nios II Processor 562
B.11.1 External Interrupt Controller 562
B.11.2 Memory Management Unit 562
B.11.3 Floating-Point Hardware 562
B.12 Concluding Remarks 563
B.13 Solved Problems 563
Problems 568
A p p e n d i x C
The ColdFire Processor 571
C.1 Memory Organization 572
C.2 Registers 572
C.3 Instructions 573
C.3.1 Addressing Modes 575
C.3.2 Move Instruction 577
C.3.3 Arithmetic Instructions 578
C.3.4 Branch and Jump Instructions 582
C.3.5 Logic Instructions 585
C.3.6 Shift Instructions 586
C.3.7 Subroutine Linkage Instructions 587
C.4 Assembler Directives 593
C.5 Example Programs 594
C.5.1 Vector Dot Product Program 594
C.5.2 String Search Program 595
C.6 Mode of Operation and Other Control Features 596
C.7 Input/Output 597
C.8 Floating-Point Operations 599
C.8.1 FMOVE Instruction 599
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C.8.2 Floating-Point Arithmetic Instructions 600
C.8.3 Comparison and Branch Instuctions 601
C.8.4 Additional Floating-Point Instructions 601
C.8.5 Example Floating-Point Program 602
C.9 Concluding Remarks 603
C.10 Solved Problems 603
Problems 608
References 609
A p p e n d i x D
The ARM Processor 611
D.1 ARM Characteristics 612
D.1.1 Unusual Aspects of the ARM Architecture 612
D.2 Register Structure 613
D.3 Addressing Modes 614
D.3.1 Basic Indexed Addressing Mode 614
D.3.2 Relative Addressing Mode 615
D.3.3 Index Modes withWriteback 616
D.3.4 Offset Determination 616
D.3.5 Register, Immediate, and Absolute Addressing Modes 618
D.3.6 Addressing Mode Examples 618
D.4 Instructions 621
D.4.1 Load and Store Instructions 621
D.4.2 Arithmetic Instructions 622
D.4.3 Move Instructions 625
D.4.4 Logic and Test Instructions 626
D.4.5 Compare Instructions 627
D.4.6 Setting Condition Code Flags 628
D.4.7 Branch Instructions 628
D.4.8 Subroutine Linkage Instructions 631
D.5 Assembly Language 635
D.5.1 Pseudoinstructions 637
D.6 Example Programs 638
D.6.1 Vector Dot Product 639
D.6.2 String Search 639
D.7 Operating Modes and Exceptions 639
D.7.1 Banked Registers 641
D.7.2 Exception Types 642
D.7.3 System Mode 644
D.7.4 Handling Exceptions 644
D.8 Input/Output 646
D.8.1 Program-Controlled I/O 646
D.8.2 Interrupt-Driven I/O 648
D.9 Conditional Execution of Instructions 648
D.10 Coprocessors 650
D.11 Embedded Applications and the Thumb ISA 651
D.12 Concluding Remarks 651
D.13 Solved Problems 652
Problems 657
References 660
A p p e n d i x E
The Intel IA-32 Architecture
661
E.1 Memory Organization 662
E.2 Register Structure 662
E.3 Addressing Modes 665
E.4 Instructions 668
E.4.1 Machine Instruction Format 670
E.4.2 Assembly-Language Notation 670
E.4.3 Move Instruction 671
E.4.4 Load-Effective-Address Instruction 671
E.4.5 Arithmetic Instructions 672
E.4.6 Jump and Loop Instructions 674
E.4.7 Logic Instructions 677
E.4.8 Shift and Rotate Instructions 678
E.4.9 Subroutine Linkage Instructions 679
E.4.10 Operations on Large Numbers 681
E.5 Assembler Directives 685
E.6 Example Programs 686
E.6.1 Vector Dot Product Program 686
E.6.2 String Search Program 686
E.7 Interrupts and Exceptions 687
E.8 Input/Output Examples 689
E.9 Scalar Floating-Point Operations 690
E.9.1 Load and Store Instructions 692
E.9.2 Arithmetic Instructions 693
E.9.3 Comparison Instructions 694
E.9.4 Additional Instructions 694
E.9.5 Example Floating-Point Program 694
E.10 Multimedia Extension (MMX) Operations 695
E.11 Vector (SIMD) Floating-Point Operations 696
E.12 Examples of Solved Problems 697
E.13 Concluding Remarks 702
Problems 702
References 703
· · · · · · (收起)
Basic Structure of
Computers 1
1.1 Computer Types 2
1.2 Functional Units 3
1.2.1 Input Unit 4
1.2.2 Memory Unit 4
1.2.3 Arithmetic and Logic Unit 5
1.2.4 Output Unit 6
1.2.5 Control Unit 6
1.3 Basic Operational Concepts 7
1.4 Number Representation and Arithmetic Operations 9
1.4.1 Integers 10
1.4.2 Floating-Point Numbers 16
1.5 Character Representation 17
1.6 Performance 17
1.6.1 Technology 17
1.6.2 Parallelism 19
1.7 Historical Perspective 19
1.7.1 The First Generation 20
1.7.2 The Second Generation 20
1.7.3 The Third Generation 21
1.7.4 The Fourth Generation 21
1.8 Concluding Remarks 22
1.9 Solved Problems 22
Problems 24
References 25
C h a p t e r 2
Instruction Set
Architecture 27
2.1 Memory Locations and Addresses 28
2.1.1 Byte Addressability 30
2.1.2 Big-Endian and Little-Endian Assignments 30
2.1.3 Word Alignment 31
2.1.4 Accessing Numbers and Characters 32
2.2 Memory Operations 32
2.3 Instructions and Instruction Sequencing 32
2.3.1 Register Transfer Notation 33
2.3.2 Assembly-Language Notation 33
2.3.3 RISC and CISC Instruction Sets 34
2.3.4 Introduction to RISC Instruction Sets 34
2.3.5 Instruction Execution and Straight-Line Sequencing 36
2.3.6 Branching 37
2.3.7 Generating Memory Addresses 40
2.4 Addressing Modes 40
2.4.1 Implementation of Variables and
Constants 41
2.4.2 Indirection and Pointers 42
2.4.3 Indexing and Arrays 45
2.5 Assembly Language 48
2.5.1 Assembler Directives 50
2.5.2 Assembly and Execution of Programs 53
2.5.3 Number Notation 54
2.6 Stacks 55
2.7 Subroutines 56
2.7.1 Subroutine Nesting and the Processor Stack 58
2.7.2 Parameter Passing 59
2.7.3 The Stack Frame 63
2.8 Additional Instructions 65
2.8.1 Logic Instructions 67
2.8.2 Shift and Rotate Instructions 68
2.8.3 Multiplication and Division 71
2.9 Dealing with 32-Bit Immediate Values 73
2.10 CISC Instruction Sets 74
2.10.1 Additional Addressing Modes 75
2.10.2 Condition Codes 77
2.11 RISC and CISC Styles 78
2.12 Example Programs 79
2.12.1 Vector Dot Product Program 79
2.12.2 String Search Program 81
2.13 Encoding of Machine Instructions 82
2.14 Concluding Remarks 85
2.15 Solved Problems 85
Problems 90
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Contents
C h a p t e r 3
Basic Input/Output 95
3.1 Accessing I/O Devices 96
3.1.1 I/O Device Interface 97
3.1.2 Program-Controlled I/O 97
3.1.3 An Example of a RISC-Style I/O Program 101
3.1.4 An Example of a CISC-Style I/O Program 101
3.2 Interrupts 103
3.2.1 Enabling and Disabling Interrupts 106
3.2.2 Handling Multiple Devices 107
3.2.3 Controlling I/O Device Behavior 109
3.2.4 Processor Control Registers 110
3.2.5 Examples of Interrupt Programs 111
3.2.6 Exceptions 116
3.3 Concluding Remarks 119
3.4 Solved Problems 119
Problems 126
C h a p t e r 4
Software 129
4.1 The Assembly Process 130
4.1.1 Two-pass Assembler 131
4.2 Loading and Executing Object Programs 131
4.3 The Linker 132
4.4 Libraries 133
4.5 The Compiler 133
4.5.1 Compiler Optimizations 134
4.5.2 Combining ProgramsWritten in Different Languages 134
4.6 The Debugger 134
4.7 Using a High-level Language for I/O Tasks 137
4.8 Interaction between Assembly Language and C Language 139
4.9 The Operating System 143
4.9.1 The Boot-strapping Process 144
4.9.2 Managing the Execution of Application Programs 144
4.9.3 Use of Interrupts in Operating Systems 146
4.10 Concluding Remarks 149
Problems 149
References 150
C h a p t e r 5
Basic Processing Unit 151
5.1 Some Fundamental Concepts 152
5.2 Instruction Execution 155
5.2.1 Load Instructions 155
5.2.2 Arithmetic and Logic Instructions 156
5.2.3 Store Instructions 157
5.3 Hardware Components 158
5.3.1 Register File 158
5.3.2 ALU 160
5.3.3 Datapath 161
5.3.4 Instruction Fetch Section 164
5.4 Instruction Fetch and Execution Steps 165
5.4.1 Branching 168
5.4.2 Waiting for Memory 171
5.5 Control Signals 172
5.6 Hardwired Control 175
5.6.1 Datapath Control Signals 177
5.6.2 Dealing with Memory Delay 177
5.7 CISC-Style Processors 178
5.7.1 An Interconnect using Buses 180
5.7.2 Microprogrammed Control 183
5.8 Concluding Remarks 185
5.9 Solved Problems 185
Problems 188
C h a p t e r 6
Pipelining 193
6.1 Basic Concept—The Ideal Case 194
6.2 Pipeline Organization 195
6.3 Pipelining Issues 196
6.4 Data Dependencies 197
6.4.1 Operand Forwarding 198
6.4.2 Handling Data Dependencies in Software 199
6.5 Memory Delays 201
6.6 Branch Delays 202
6.6.1 Unconditional Branches 202
6.6.2 Conditional Branches 204
6.6.3 The Branch Delay Slot 204
6.6.4 Branch Prediction 205
6.7 Resource Limitations 209
6.8 Performance Evaluation 209
6.8.1 Effects of Stalls and Penalties 210
6.8.2 Number of Pipeline Stages 212
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Contents
6.9 Superscalar Operation 212
6.9.1 Branches and Data Dependencies 214
6.9.2 Out-of-Order Execution 215
6.9.3 Execution Completion 216
6.9.4 Dispatch Operation 217
6.10 Pipelining in CISC Processors 218
6.10.1 Pipelining in ColdFire Processors 219
6.10.2 Pipelining in Intel Processors 219
6.11 Concluding Remarks 220
6.12 Examples of Solved Problems 220
Problems 222
References 226
C h a p t e r 7
Input/Output Organization 227
7.1 Bus Structure 228
7.2 Bus Operation 229
7.2.1 Synchronous Bus 230
7.2.2 Asynchronous Bus 233
7.2.3 Electrical Considerations 236
7.3 Arbitration 237
7.4 Interface Circuits 238
7.4.1 Parallel Interface 239
7.4.2 Serial Interface 243
7.5 Interconnection Standards 247
7.5.1 Universal Serial Bus (USB) 247
7.5.2 FireWire 251
7.5.3 PCI Bus 252
7.5.4 SCSI Bus 256
7.5.5 SATA 258
7.5.6 SAS 258
7.5.7 PCI Express 258
7.6 Concluding Remarks 260
7.7 Solved Problems 260
Problems 263
References 266
C h a p t e r 8
The Memory System 267
8.1 Basic Concepts 268
8.2 Semiconductor RAM Memories 270
8.2.1 Internal Organization of Memory Chips 270
8.2.2 Static Memories 271
8.2.3 Dynamic RAMs 274
8.2.4 Synchronous DRAMs 276
8.2.5 Structure of Larger Memories 279
8.3 Read-only Memories 282
8.3.1 ROM 283
8.3.2 PROM 283
8.3.3 EPROM 284
8.3.4 EEPROM 284
8.3.5 Flash Memory 284
8.4 Direct Memory Access 285
8.5 Memory Hierarchy 288
8.6 Cache Memories 289
8.6.1 Mapping Functions 291
8.6.2 Replacement Algorithms 296
8.6.3 Examples of Mapping Techniques 297
8.7 Performance Considerations 300
8.7.1 Hit Rate and Miss Penalty 301
8.7.2 Caches on the Processor Chip 302
8.7.3 Other Enhancements 303
8.8 Virtual Memory 305
8.8.1 Address Translation 306
8.9 Memory Management Requirements 310
8.10 Secondary Storage 311
8.10.1 Magnetic Hard Disks 311
8.10.2 Optical Disks 317
8.10.3 Magnetic Tape Systems 322
8.11 Concluding Remarks 323
8.12 Solved Problems 324
Problems 328
References 332
C h a p t e r 9
Arithmetic 335
9.1 Addition and Subtraction of Signed Numbers 336
9.1.1 Addition/Subtraction Logic Unit 336
9.2 Design of Fast Adders 339
9.2.1 Carry-Lookahead Addition 340
9.3 Multiplication of Unsigned Numbers 344
9.3.1 Array Multiplier 344
9.3.2 Sequential Circuit Multiplier 346
9.4 Multiplication of Signed Numbers 346
9.4.1 The Booth Algorithm 348
9.5 Fast Multiplication 351
9.5.1 Bit-Pair Recoding of Multipliers 352
9.5.2 Carry-Save Addition of Summands 353
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9.5.3 Summand Addition Tree using 3-2 Reducers 355
9.5.4 Summand Addition Tree using 4-2 Reducers 357
9.5.5 Summary of Fast Multiplication 359
9.6 Integer Division 360
9.7 Floating-Point Numbers and Operations 363
9.7.1 Arithmetic Operations on Floating-Point Numbers 367
9.7.2 Guard Bits and Truncation 368
9.7.3 Implementing Floating-Point Operations 369
9.8 Decimal-to-Binary Conversion 372
9.9 Concluding Remarks 372
9.10 Solved Problems 374
Problems 377
References 383
C h a p t e r 10
Embedded Systems 385
10.1 Examples of Embedded Systems 386
10.1.1 Microwave Oven 386
10.1.2 Digital Camera 387
10.1.3 Home Telemetry 390
10.2 Microcontroller Chips for Embedded Applications 390
10.3 A Simple Microcontroller 392
10.3.1 Parallel I/O Interface 392
10.3.2 Serial I/O Interface 395
10.3.3 Counter/Timer 397
10.3.4 Interrupt-Control Mechanism 399
10.3.5 Programming Examples 399
10.4 Reaction Timer—AComplete Example 401
10.5 Sensors and Actuators 407
10.5.1 Sensors 407
10.5.2 Actuators 410
10.5.3 Application Examples 411
10.6 Microcontroller Families 412
10.6.1 Microcontrollers Based on the Intel 8051 413
10.6.2 Freescale Microcontrollers 413
10.6.3 ARM Microcontrollers 414
10.7 Design Issues 414
10.8 Concluding Remarks 417
Problems 418
References 420
C h a p t e r 11
System-on-a-Chip—A Case Study 421
11.1 FPGA Implementation 422
11.1.1 FPGA Devices 423
11.1.2 Processor Choice 423
11.2 Computer-Aided Design Tools 424
11.2.1 Altera CAD Tools 425
11.3 Alarm Clock Example 428
11.3.1 User’s View of the System 428
11.3.2 System Definition and Generation 429
11.3.3 Circuit Implementation 430
11.3.4 Application Software 431
11.4 Concluding Remarks 440
Problems 440
References 441
C h a p t e r 12
Parallel Processing and Performance 443
12.1 Hardware Multithreading 444
12.2 Vector (SIMD) Processing 445
12.2.1 Graphics Processing Units (GPUs) 448
12.3 Shared-Memory Multiprocessors 448
12.3.1 Interconnection Networks 450
12.4 Cache Coherence 453
12.4.1 Write-Through Protocol 453
12.4.2 Write-Back protocol 454
12.4.3 Snoopy Caches 454
12.4.4 Directory-Based Cache Coherence 456
12.5 Message-Passing Multicomputers 456
12.6 Parallel Programming for Multiprocessors 456
12.7 Performance Modeling 460
12.8 Concluding Remarks 461
Problems 462
References 463
A p p e n d i x A
Logic Circuits 465
A.1 Basic Logic Functions
A.1.1 Electronic Logic Gates 469
A.2 Synthesis of Logic Functions 470
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A.3 Minimization of Logic Expressions 472
A.3.1 Minimization using Karnaugh Maps 475
A.3.2 Don’t-Care Conditions 477
A.4 Synthesis with NAND and NOR Gates 479
A.5 Practical Implementation of Logic Gates 482
A.5.1 CMOS Circuits 484
A.5.2 Propagation Delay 489
A.5.3 Fan-In and Fan-Out Constraints 490
A.5.4 Tri-State Buffers 491
A.6 Flip-Flops 492
A.6.1 Gated Latches 493
A.6.2 Master-Slave Flip-Flop 495
A.6.3 Edge Triggering 498
A.6.4 T Flip-Flop 498
A.6.5 JK Flip-Flop 499
A.6.6 Flip-Flops with Preset and Clear 501
A.7 Registers and Shift Registers 502
A.8 Counters 503
A.9 Decoders 505
A.10 Multiplexers 506
A.11 Programmable Logic Devices (PLDs) 509
A.11.1 Programmable Logic Array (PLA) 509
A.11.2 Programmable Array Logic (PAL) 511
A.11.3 Complex Programmable Logic Devices (CPLDs) 512
A.12 Field-Programmable Gate Arrays 514
A.13 Sequential Circuits 516
A.13.1 Design of an Up/Down Counter as a Sequential Circuit 516
A.13.2 Timing Diagrams 519
A.13.3 The Finite State Machine Model 520
A.13.4 Synthesis of Finite State Machines 521
A.14 Concluding Remarks 522
Problems 522
References 528
A p p e n d i x B
The Altera Nios II
Processor 529
B.1 Nios II Characteristics 530
B.2 General-Purpose Registers 531
B.3 Addressing Modes 532
B.4 Instructions 533
B.4.1 Notation 533
B.4.2 Load and Store Instructions 534
B.4.3 Arithmetic Instructions 536
B.4.4 Logic Instructions 537
B.4.5 Move Instructions 537
B.4.6 Branch and Jump Instructions 538
B.4.7 Subroutine Linkage Instructions 541
B.4.8 Comparison Instructions 545
B.4.9 Shift Instructions 546
B.4.10 Rotate Instructions 547
B.4.11 Control Instructions 548
B.5 Pseudoinstructions 548
B.6 Assembler Directives 549
B.7 Carry and Overflow Detection 551
B.8 Example Programs 553
B.9 Control Registers 553
B.10 Input/Output 555
B.10.1 Program-Controlled I/O 556
B.10.2 Interrupts and Exceptions 556
B.11 Advanced Configurations of Nios II Processor 562
B.11.1 External Interrupt Controller 562
B.11.2 Memory Management Unit 562
B.11.3 Floating-Point Hardware 562
B.12 Concluding Remarks 563
B.13 Solved Problems 563
Problems 568
A p p e n d i x C
The ColdFire Processor 571
C.1 Memory Organization 572
C.2 Registers 572
C.3 Instructions 573
C.3.1 Addressing Modes 575
C.3.2 Move Instruction 577
C.3.3 Arithmetic Instructions 578
C.3.4 Branch and Jump Instructions 582
C.3.5 Logic Instructions 585
C.3.6 Shift Instructions 586
C.3.7 Subroutine Linkage Instructions 587
C.4 Assembler Directives 593
C.5 Example Programs 594
C.5.1 Vector Dot Product Program 594
C.5.2 String Search Program 595
C.6 Mode of Operation and Other Control Features 596
C.7 Input/Output 597
C.8 Floating-Point Operations 599
C.8.1 FMOVE Instruction 599
xvi Contents
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C.8.2 Floating-Point Arithmetic Instructions 600
C.8.3 Comparison and Branch Instuctions 601
C.8.4 Additional Floating-Point Instructions 601
C.8.5 Example Floating-Point Program 602
C.9 Concluding Remarks 603
C.10 Solved Problems 603
Problems 608
References 609
A p p e n d i x D
The ARM Processor 611
D.1 ARM Characteristics 612
D.1.1 Unusual Aspects of the ARM Architecture 612
D.2 Register Structure 613
D.3 Addressing Modes 614
D.3.1 Basic Indexed Addressing Mode 614
D.3.2 Relative Addressing Mode 615
D.3.3 Index Modes withWriteback 616
D.3.4 Offset Determination 616
D.3.5 Register, Immediate, and Absolute Addressing Modes 618
D.3.6 Addressing Mode Examples 618
D.4 Instructions 621
D.4.1 Load and Store Instructions 621
D.4.2 Arithmetic Instructions 622
D.4.3 Move Instructions 625
D.4.4 Logic and Test Instructions 626
D.4.5 Compare Instructions 627
D.4.6 Setting Condition Code Flags 628
D.4.7 Branch Instructions 628
D.4.8 Subroutine Linkage Instructions 631
D.5 Assembly Language 635
D.5.1 Pseudoinstructions 637
D.6 Example Programs 638
D.6.1 Vector Dot Product 639
D.6.2 String Search 639
D.7 Operating Modes and Exceptions 639
D.7.1 Banked Registers 641
D.7.2 Exception Types 642
D.7.3 System Mode 644
D.7.4 Handling Exceptions 644
D.8 Input/Output 646
D.8.1 Program-Controlled I/O 646
D.8.2 Interrupt-Driven I/O 648
D.9 Conditional Execution of Instructions 648
D.10 Coprocessors 650
D.11 Embedded Applications and the Thumb ISA 651
D.12 Concluding Remarks 651
D.13 Solved Problems 652
Problems 657
References 660
A p p e n d i x E
The Intel IA-32 Architecture
661
E.1 Memory Organization 662
E.2 Register Structure 662
E.3 Addressing Modes 665
E.4 Instructions 668
E.4.1 Machine Instruction Format 670
E.4.2 Assembly-Language Notation 670
E.4.3 Move Instruction 671
E.4.4 Load-Effective-Address Instruction 671
E.4.5 Arithmetic Instructions 672
E.4.6 Jump and Loop Instructions 674
E.4.7 Logic Instructions 677
E.4.8 Shift and Rotate Instructions 678
E.4.9 Subroutine Linkage Instructions 679
E.4.10 Operations on Large Numbers 681
E.5 Assembler Directives 685
E.6 Example Programs 686
E.6.1 Vector Dot Product Program 686
E.6.2 String Search Program 686
E.7 Interrupts and Exceptions 687
E.8 Input/Output Examples 689
E.9 Scalar Floating-Point Operations 690
E.9.1 Load and Store Instructions 692
E.9.2 Arithmetic Instructions 693
E.9.3 Comparison Instructions 694
E.9.4 Additional Instructions 694
E.9.5 Example Floating-Point Program 694
E.10 Multimedia Extension (MMX) Operations 695
E.11 Vector (SIMD) Floating-Point Operations 696
E.12 Examples of Solved Problems 697
E.13 Concluding Remarks 702
Problems 702
References 703
· · · · · · (收起)
读后感
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我拿到这本《计算机组成与嵌入式系统》的时候，第一感觉就是它似乎能帮我解答很多关于“机器如何思考”的疑问。我一直对那些能够独立思考、执行复杂任务的智能设备感到好奇，比如自动驾驶汽车、智能家居系统，以及那些隐藏在幕后的工业控制系统。我希望这本书能为我揭示这些系统的“大脑”是如何运作的。特别是对于嵌入式系统，我总觉得它们就像是为特定任务量身定制的“专用大脑”，与通用计算机有着截然不同的设计思路。我希望书中能深入讲解嵌入式系统的硬件特性，比如处理器的选型、内存的类型和容量、外设接口的设计，以及如何根据功耗、成本和性能的要求进行权衡。我也很期待书中关于底层软件的描述，比如如何编写驱动程序，如何与硬件直接交互，以及如何利用汇编语言或者低级编程语言来优化性能。
评分拿到《计算机组成与嵌入式系统》这本书，我带着一种“探险”的心情。我一直觉得，计算机硬件就像是一个庞大而精密的机器，而嵌入式系统则是这个机器上那些“隐藏在角落里”，却又至关重要的“齿轮”。我希望这本书能够带领我深入这个“机器”的内部，去了解它的每一个“部件”是如何协作的。我尤其想知道，CPU是如何解读和执行一条条指令的，内存又是如何存储和检索数据的。对于嵌入式系统，我希望能够理解它们为什么要在如此小的空间里集成如此多的功能，以及在设计过程中，开发者需要考虑哪些独特的挑战。比如，如何确保系统的可靠性和安全性，如何在极端的环境下（如高温、低温、高湿）保持稳定运行，以及如何在有限的成本下实现高性能。我期待书中能有关于嵌入式软件开发的一些入门级介绍，即使不深入，但能让我看到一个大致的框架。
评分当我拿到《计算机组成与嵌入式系统》这本书时，我心里就想着，这下终于有机会能系统地了解计算机的“骨架”和“灵魂”了。我一直对数字电路背后的逻辑非常着迷，从简单的逻辑门到复杂的组合逻辑和时序逻辑，我觉得这是理解一切的基础。我希望这本书能够从最基础的数字系统理论讲起，然后逐步过渡到CPU的设计，包括指令集、数据通路、控制单元等。而嵌入式系统对我来说，更是充满了神秘感。我好奇它们是怎么做到“麻雀虽小，五脏俱全”的，又是如何做到低功耗、高效率的。我希望书中能够详细讲解微控制器（MCU）的架构，以及各种外设接口（如GPIO、UART、SPI、I2C）的工作原理和应用。我更期待它能提供一些关于嵌入式系统开发流程的介绍，比如交叉编译、固件下载、调试方法等，让我能窥探到实际开发的全貌。
评分这本书我拿到手的时候，真的是满怀期待。我一直觉得，要想真正理解现代电子设备的“心脏”是如何跳动的，就得深入到计算机最底层的原理。我之前也零散地看过一些关于CPU、内存、总线之类的资料，但总觉得不成体系，知识点之间就像散落的珍珠，串不起来。我希望这本书能够提供一个清晰的脉络，从最基本的逻辑门开始，逐步构建起一个完整的计算机体系结构。我尤其关心的是，如何从一堆0和1的组合，最终变成我们能够操作的各种软件应用，这个“转化”的过程是如何实现的。而且，对于嵌入式系统，我一直很好奇它们是如何在资源极其有限的条件下，完成如此复杂的功能。比如，一个小小的智能手表，是如何通过微小的芯片，连接网络、显示信息、监测心率的？这本书会不会触及到这些“黑科技”背后的设计哲学和技术细节？我希望它不仅能告诉我“是什么”，更能告诉我“为什么”和“怎么做”。
评分拿到《计算机组成与嵌入式系统》这本书，我最看重的是它能否在理论深度和实践指导之间找到一个绝佳的平衡点。我不是那种只满足于“知其然”的读者，我更希望能够“知其所以然”。这意味着，我希望书中能够详细阐述各种硬件组件的工作原理，比如CPU的指令集架构、流水线技术、缓存机制，以及不同类型内存的工作方式和性能差异。更重要的是，我期待它能够将这些理论知识与嵌入式系统开发紧密结合。例如，如何根据不同的应用场景，选择合适的微控制器，如何进行高效的硬件资源管理，如何优化代码以适应有限的内存和处理能力。我对书中关于实时操作系统（RTOS）的部分特别感兴趣，了解它们是如何管理任务、调度资源，以及如何保证系统在严格的时间约束下稳定运行。如果这本书能够提供一些实际的项目案例，或者指导如何进行硬件调试，那就更完美了。
评分再次被学校教材坑了一波
评分再次被学校教材坑了一波
评分再次被学校教材坑了一波
评分再次被学校教材坑了一波
评分再次被学校教材坑了一波
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