About the Author
Samir Palnitkar is currently the President of Jambo Systems, Inc., a leading ASIC design and verification services company which specializes in high-end designs for microprocessor, networking, and communications applications. Mr. Palnitkar is a serial entrepreneur. He was the founder of Integrated Intellectual Property, Inc., an ASIC company that was acquired by Lattice Semiconductor, Inc. Later he founded Obongo, Inc., an e-commerce software firm that was acquired by AOL Time Warner, Inc.
Mr. Palnitkar holds a Bachelor of Technology in Electrical Engineering from Indian Institute of Technology, Kanpur, a Master's in Electrical Engineering from University of Washington, Seattle, and an MBA degree from San Jose State University, San Jose, CA.
Mr. Palnitkar is a recognized authority on Verilog HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARCTM Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Motorola, National, Advanced Micro Devices, and Standard Microsystems.
Mr. Palnitkar was also a leading member of the group that first experimented with cycle-based simulation technology on joint projects with simulator companies. He has extensive experience with a variety of EDA tools such as Verilog-NC, Synopsys VCS, Specman, Vera, System Verilog, Synopsys, SystemC, Verplex, and Design Data Management Systems.
Mr. Palnitkar is the author of three US patents, one for a novel method to analyze finite state machines, a second for work on cycle-based simulation technology and a third(pending approval) for a unique e-commerce tool. He has also published several technical papers. In his spare time, Mr. Palnitkar likes to play cricket, read books, and travel the world.
Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. Verilog HDL is a hardware description language (with a user community of more than 50,000 active designers) used to design and document electronic systems. This completely updated reference progresses from basic to advanced concepts in digital design, including timing simulation, switch level modeling, PLI, and logic synthesis.
發表於2024-12-29
Verilog HDL 2024 pdf epub mobi 電子書 下載
我覺得學習數字設計有兩個思路: 將數字設計的核心思路和語言混在一起學,可以考慮夏老師的高教那本書。 將這兩個概念分開來學。我覺得這本在verilog語言上講解的非常清晰、簡明。針對VHDL推薦Volnei A. Pedroni的那邊,風格十分接近。
評分隻要有C語言和少量數電基礎的就可以看得懂。 適閤沒有Verilog基礎的初學者。 看過的第一本關於電子設計的書。 在網上搜這本書時發現譯者夏宇聞好像是EDA這方麵挺有名氣的一個老師。 字數不夠?
評分我覺得學習數字設計有兩個思路: 將數字設計的核心思路和語言混在一起學,可以考慮夏老師的高教那本書。 將這兩個概念分開來學。我覺得這本在verilog語言上講解的非常清晰、簡明。針對VHDL推薦Volnei A. Pedroni的那邊,風格十分接近。
評分我覺得學習數字設計有兩個思路: 將數字設計的核心思路和語言混在一起學,可以考慮夏老師的高教那本書。 將這兩個概念分開來學。我覺得這本在verilog語言上講解的非常清晰、簡明。針對VHDL推薦Volnei A. Pedroni的那邊,風格十分接近。
評分隻要有C語言和少量數電基礎的就可以看得懂。 適閤沒有Verilog基礎的初學者。 看過的第一本關於電子設計的書。 在網上搜這本書時發現譯者夏宇聞好像是EDA這方麵挺有名氣的一個老師。 字數不夠?
圖書標籤: 數字IC設計 IC 計算機 電子 tech VHDL
verilog最好的入門資料
評分verilog最好的入門資料
評分verilog最好的入門資料
評分verilog最好的入門資料
評分極好的verilog書,幾乎沒有一句廢話,可以用來入門,也可用來快速復習!短時間掌握verilog必備的書.夏宇聞等已也把此書翻譯成中文瞭,譯的還算可以.
Verilog HDL 2024 pdf epub mobi 電子書 下載