Dake Liu is Professor of the chair and the Director of Computer Engineering Division, Department of Electrical Engineering at Linköping University. He received his Ph.D. (Tekn. Dr.) degree from Linköping University in Feb. 1995.

Dake Liu performs his research of Computer architecture focusing on architectures of application specific instruction set processors (ASIP) and on-chip multi-core integrations based on VLSI. His research goal is to explore different processor architectures and inter processor architectures.

Dake Liu is the co-founder of FreeHand DSP AB, (VIA tech Sweden AB, Liljeholmsstranden 5, S-117 43, Stockholm). Freehad DSP was acquired by VIA technologies in 2001. Dake Liu is the co-founder of Coresonic AB. Dake Liu was a senior ASIC designer and low power design specialist in Ericsson Microelectronics, Stockholm, Sweden (Infineon Technologies Wireless Solutions Sweden AB) since 1995 to 1998.

劉大可早年畢業於北方交通大學。後赴瑞典留學，於1992和1994年分彆獲得瑞典林雪平大學副博士、工學博士學位。劉大可曾任愛立信瑞典(Ericsson)微電子集團高級研究員及高級設計師，現兼任威盛瑞典董事和威盛瑞典資深首席科學官。作為集成電路和處理器研究與設計方麵的著名專傢,劉大可在移動通訊手機數字信號處理係統、移動通訊基帶數字信號處理器、互聯網關語音係統、可編程專用網絡處理器、超高速圖片(JPEG)壓縮數字信號處理器、數字信號處理器通用集成設計環境等方麵取得瞭世界領先的科研成果。

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This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers.

Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples.

* Instruction set design for application specific processors based on fast application profiling

* Micro architecture design methodology

* Micro architecture design details based on real examples

* Extendable architecture design protocols

* Design for efficient memory sub systems (minimizing on chip memory and cost)

* Real example designs based on extensive, industrial experiences