Verification Methodology Manual for SystemVerilog

出版者:Springer

作者:Janick Bergeron

页数:524

出版时间:2005-09-28

价格:USD 129.00

装帧:Hardcover

isbn号码:9780387255385

图书标签:VerificationSystemVerilogVMM电子逻辑综合编程tech-softwaresoc

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point tools, most with their own languages and methodologies. Fortunately, a solution is at hand. SystemVerilog is a unified language that serves both design and verification engineers by including RTL design constructs, assertions and a rich set of verification constructs. SystemVerilog is an industry standard that is well supported by a wide range of verification tools and platforms. A single language fosters the development of a unified simulation-based verification tool or platform. Consolidation of point tools into a unified platform and convergence to a unified language enable the development of a unified verification methodology that can be used on a wide range of SoC projects. ARM and Synopsys have worked together to define just such a methodology in the Verification Methodology Manual for SystemVerilog. This book is based upon best verification practices by ARM, Synopsys and their customers. Verification Methodology Manual for SystemVerilog is a blueprint for verification success, guiding SoC teams in building a reusable verification environment taking full advantage of design-for-verification techniques, constrained-random stimulus generation, coverage-driven verification, formal verification and other advanced technologies to help solve their current and future verification problems. This book is appropriate for anyone involved in the design or verification of a complex chip or anyone who would like to know more about the capabilities of SystemVerilog. Following the Verification Methodology Manual for SystemVerilog will give SoC development teams and project managers the confidence needed to tape out a complex design, secure in the knowledge that the chip will function correctly in the real world.

读后感

静下心来想好好读一读这本书，读不了几页就给呛得受不了了。 不是说原书好不好--相信一定非常好，而是像很多很多中国人翻译的外文技术经典一样，翻译得太烂了。你会以为那是恰好其文字也正好是方块象形文字的另一种语言。 夏老先生自己写的中文书其实还是不错的，但是何苦来呢...  

静下心来想好好读一读这本书，读不了几页就给呛得受不了了。 不是说原书好不好--相信一定非常好，而是像很多很多中国人翻译的外文技术经典一样，翻译得太烂了。你会以为那是恰好其文字也正好是方块象形文字的另一种语言。 夏老先生自己写的中文书其实还是不错的，但是何苦来呢...  

感觉这本书适合有相当经验的读者,初学者不太适用.先看看<<systemverilog硬件设计与建模>>

静下心来想好好读一读这本书，读不了几页就给呛得受不了了。 不是说原书好不好--相信一定非常好，而是像很多很多中国人翻译的外文技术经典一样，翻译得太烂了。你会以为那是恰好其文字也正好是方块象形文字的另一种语言。 夏老先生自己写的中文书其实还是不错的，但是何苦来呢...  

感觉这本书适合有相当经验的读者,初学者不太适用.先看看<<systemverilog硬件设计与建模>>

用户评价

VMM虽然已经过时了，但是方法学没有过时。。。

VMM虽然已经过时了，但是方法学没有过时。。。

VMM虽然已经过时了，但是方法学没有过时。。。

VMM虽然已经过时了，但是方法学没有过时。。。

VMM虽然已经过时了，但是方法学没有过时。。。